1. Field of the Invention
The present invention relates to a chip stack package, and more particularly, to a chip stack package including chips that are stacked at a wafer level or a chip level.
2. Description of the Related Art
A recent trend of the semiconductor industry is to make inexpensive semiconductor products compact, thin, light, fast, multifunctional and highly-efficient, so as to have high reliability. To achieve this, a package technology has been used as one of the important technologies for designing such semiconductor products.
For example, a chip stack package is a chip-sized package, and is configured by stacking chips at a wafer level or a chip level if necessary. Since chips are stacked on a wiring substrate, a chip stack package can have a high stack density of chips. In addition, since different kinds of chips (e.g., a memory chip and a control chip) can be stacked, the chip stack package is used as a system-in-package (SiP).
In a chip stack package, a plurality of chips needs to be electrically connected to one another, wherein the chips are disposed on upper and lower portions of the chip stack package. Accordingly, the chip stack package includes a through via electrode formed through the chips so that the chips can be electrically connected to each other via the through via electrode. However, since the chips are connected to each other using the through via electrode in the chip stack package, the electrical characteristics of the chip stack package can deteriorate.